1. Field of the Invention
Generally, the present disclosure relates to the manufacture of FET semiconductor devices, and, more specifically, to various methods of forming alternative material fins with reduced defect density for a FinFET semiconductor device that includes performing an ion implantation/anneal defect generation process.
2. Description of the Related Art
The fabrication of advanced integrated circuits, such as CPU's, storage devices, ASIC's (application specific integrated circuits) and the like, requires the formation of a large number of circuit elements in a given chip area according to a specified circuit layout, wherein so-called metal oxide field effect transistors (MOSFETs or FETs) represent one important type of circuit element that substantially determines performance of the integrated circuits. A conventional FET is a planar device that typically includes a source region, a drain region, and a channel region that is positioned between the source region and the drain region, and a gate electrode positioned above the channel region. Current flow through the FET is controlled by controlling the voltage applied to the gate electrode. For example, for an NMOS device, if there is no voltage applied to the gate electrode, then there is no current flow through the NMOS device (ignoring undesirable leakage currents, which are relatively small). However, when an appropriate positive voltage is applied to the gate electrode, the channel region of the NMOS device becomes conductive, and electrical current is permitted to flow between the source region and the drain region through the conductive channel region.
To improve the operating speed of FETs, and to increase the density of FETs on an integrated circuit device, device designers have greatly reduced the physical size of FETs over the past decades. More specifically, the channel length of FETs has been significantly decreased, which has resulted in improving the switching speed and in lowering operation currents and voltages of FETs. However, decreasing the channel length of a FET also decreases the distance between the source region and the drain region. In some cases, this decrease in the separation between the source and the drain makes it difficult to efficiently inhibit the electrical potential of the source region and the channel from being adversely affected by the electrical potential of the drain. This is sometimes referred to as a so-called short channel effect, wherein the characteristic of the FET as an active switch is degraded.
In contrast to a planar FET, there are so-called devices, such as an illustrative FinFET device, which is a three-dimensional structure. FIG. 1A is a perspective view of an illustrative prior art FinFET semiconductor device A that is formed above a semiconductor substrate B. The device A includes three illustrative fins C, a gate structure D, sidewall spacers E and a gate cap layer F. The gate structure D is typically comprised of a layer of insulating material (not separately shown), e.g., a layer of high-k insulating material, and one or more conductive material layers that serve as the gate electrode for the device A. In this example, the fins C are comprised of a substrate fin portion C1 and an alternative fin material portion C2. The substrate fin portion C1 may be made of silicon, i.e., the same material as the substrate, and the alternative fin material portion C2 may be made of a material other than the substrate material, for example, silicon-germanium, germanium, II-V materials, etc. The fins C have a three-dimensional configuration: a height H, a width W and an axial length L. The axial length L corresponds to the direction of current travel in the device A when it is operational. The portions of the fins C covered by the gate structure D are the channel regions of the FinFET device A.
Device manufacturers are under constant pressure to produce integrated circuit products with increased performance and lower production costs relative to previous device generations. Thus, device designers spend a great amount of time and effort to maximize device performance while seeking ways to reduce manufacturing costs and improve manufacturing reliability. As it relates to devices, device designers have spent many years and employed a variety of techniques in an effort to improve the performance capability and reliability of such devices. Device designers are currently investigating using alternative semiconductor materials, such as silicon-germanium, germanium and so-called III-V materials, to manufacture FinFET devices which are intended to enhance the performance capabilities of such devices, e.g., to enable low-voltage operation.
However, the integration of such alternative materials on silicon substrates (the dominant substrates used in the industry) is a non-trivial matter due to, among other issues, the large difference in lattice constants between such alternative materials and silicon. That is, with reference to FIG. 1A, the lattice constant of the alternative fin material portion C2 of the fin C may be greater than the lattice constant of the substrate fin portion C1 of the fin C. As a result of this mismatch in lattice constants, an unacceptable number of defects may be formed or created in the alternative fin material portion C2. As used herein and in the claims attached hereto, a “defect” is a misfit dislocation in the crystalline structure of the alternative fin material portion C2 of the fin C.
With respect to forming such lattice-constant-mismatched materials on one another, there is a concept that is generally referred to as the “critical thickness” of a material. Critical thickness is defined as the minimum thickness of a completely strained heterostructure material substantially without any defects such as dislocations. In the case where a material is formed to a thickness that is less than its critical thickness, the material stays in a “stable” state, wherein it is in a fully-strained condition that is 100% strained in at least one crystalline plane of the material. In the case where a material is formed to a thickness that is greater than its critical thickness, the material is in a “relaxed-with-defects” state and it has zero or partial strain in all crystalline planes. However, the “critical thickness” of a material may not be constant for all situations. For example, when the growth temperature used in forming the material is very low, the resulting material could be in a “metastable” state where it remains fully strained to the same level as a material in the above-described stable state, but the metastable material is in an unstable condition wherein it will relax readily, with the resulting formation of defects, upon application of a relatively large amount of thermal energy to the metastable material.
FIG. 1B is a graph taken from an article entitled “Silicon-Germanium Strained Layer Materials in Microelectronics” by Douglas J. Paul that was published in Advanced Materials magazine (11(3), 101-204 (1999)). FIG. 1B graphically depicts these three conditions for silicon germanium materials (Si1-xGex; x=0-1). The vertical axis is the critical thickness in nanometers. The horizontal axis is the concentration of germanium in the silicon-germanium material. At the leftmost point on the horizontal axis is pure silicon (Ge concentration equals 0.0). At the rightmost point on the horizontal axis is pure germanium (Ge concentration equals 1.0). The two curves R and S define the stable, metastable and relaxed-with-defects regions for silicon-germanium materials having differing germanium concentration levels. Above and to the right of curve R are materials that are in the relaxed-with-defects condition. Below and to the left of curve S are materials that are in the stable condition. The region between the two curves R and S defines the region where materials are in the metastable condition.
To add more precision to the terminology regarding critical thickness, the term “stable critical thickness” will be used herein and in the attached claims to refer to a maximum thickness of a material at which it may be formed in a substantially defect-free and “fully-strained” condition above a substrate material, i.e., in an unconfined growth environment. Additionally, as used herein and in the attached claims, the term “metastable critical thickness” will be used to refer to a maximum thickness of a material at which it may be formed in a metastable condition above a substrate material, i.e., in certain growth environments. As noted above, a material in the metastable condition is not stable and could be relaxed (with the associated defect being formed) relatively quickly when the environment is changed, e.g., when the metastable material is annealed. Nevertheless, a material that is in a metastable state is still fully strained and substantially defect-free.
With reference to FIG. 1B, a layer of pure germanium (Ge concentration equal to 1.0) may be in the stable condition at a thickness up to about 1-2 nm (point CT1) and it may be in a metastable condition for thicknesses between about 2-4 nm (point CT2). Above a thickness of about 4 nm, a layer of pure germanium will be in the relaxed-with-defects condition. In contrast, a layer of silicon-germanium with a 50% concentration of germanium may be in the stable condition at thicknesses up to about 4 nm (point CT3) and it may be in a metastable condition for thicknesses between about 4-30 nm (point CT4). Above a thickness of about 30 nm, a layer of silicon-germanium with a 50% concentration of germanium will be in the relaxed-with-defects condition. Again, this critical thickness is the thickness of a material as it is grown on a planar, non-confined non-restricted surface of another material.
A material that is in the relaxed-with-defects condition is a material that contains visible defects that are indicative that the material has relaxed to the point where defects have been formed in the material. For example, FIG. 1C is a TEM photograph of a cross-sectioned fin of a FinFET device (taken along the axial length “L” of the fin) wherein the substrate fin C1 is comprised of silicon and the alternative fin material portion C2 of the fin is comprised of silicon-germanium with a 50% concentration of germanium (SiGe0.5). The axial length direction “L” and height direction “H” of the fin are indicated in FIG. 1C. In this example, the thickness or height “H” of the alternative fin material C2 was about 30 nm, a thickness greater than the metastable critical thickness for this material (which is about 30 nm according to FIG. 1B). Accordingly, the alternative fin material C2 is in the relaxed-with-defects condition and defects are visible throughout the alternative fin material C2 and at the interface between the materials C1/C2. Thus, in this example, the alternative fin material C2 shown in FIG. 1C is fully relaxed in all three directions—axial length L, height H and width W, i.e., it is in the relaxed-with-defects condition.
As another example, a substantially pure layer of germanium (Ge concentration equal to 1.0) may have a maximum stable critical thickness of about 1-2 nm when formed on a silicon substrate, i.e., in an unconfined growth environment. A substantially pure layer of germanium formed to a thickness of 1-2 nm or less would be considered to be a stable, fully-strained layer of germanium. In contrast, a layer of silicon-germanium with a concentration of germanium of about fifty percent (SiGe0.5) may have a maximum stable critical thickness of about 4 nm and still be substantially free of defects, i.e., in a stable condition. However, such a layer of germanium or silicon-germanium would no longer be considered to be a stable material if grown beyond their respective maximum stable critical thickness values. When such a layer of material is grown to a thickness that is greater than its maximum stable critical thickness but less than its maximum metastable thickness, it is considered to be a metastable material that, when heated for example, would start experiencing some degree of relaxation, i.e., there will be some degree of strain relaxation along one or more of the crystalline planes of the material and there may or may not be some defects present at or near the interface between the alternative fin material and the substrate fin. Thus, in general, the formation of stable, fully-strained, substantially defect-free alternative materials on silicon is limited to very thin layers of the alternative materials.
The presence of defects in an alternative-material fin structure would be detrimental to device operations. One process that has been investigated for use in forming such alternative fin materials is known as aspect-ratio-trapping (ART). Some basic aspects of the ART process will now be discussed with reference to FIGS. 1D-1H. FIG. 1D is a cross-sectional view (in the gate width direction (W)) of an illustrative FinFET device 10 after several process operations were performed. First, one or more etching processes, e.g., anisotropic etching processes, were performed through a patterned etch mask (not shown) to define a plurality of fin-formation trenches 12X in the substrate 12. The formation of the trenches 12X results in the formation of a plurality of initial fin structures 16. Thereafter, a layer of insulating material 14, such as a layer of silicon dioxide, was formed in the trenches 12X between the fins 16. The layer of insulating material 14 was blanket-deposited across the device so as to over-fill the trenches 12X. Thereafter, a chemical mechanical polishing (CMP) process was performed to planarize the upper surface 14U of the layer of material 14 with the upper surface 16U of the fins 16.
Next, as shown in FIG. 1E, one or more etching processes were performed to remove substantially all or part of the fins 16 and thereby expose a surface 12S of the substrate 12. This process defines a plurality of trenches 14T in the layer of insulating material 14.
Next, as shown in FIG. 1F, a strain-relaxed buffer (SRB) material 18, e.g., silicon-germanium, was initially formed in the trenches 14T, typically so as to overfill the trenches 14T. Thereafter, a CMP/etch-back process was performed on SRB material 18 so as to leave only the desired amount of the SRB material 18 in the trenches 14T. At that point, an anneal process was performed on the device 10. The anneal process results in the formation of simplistically depicted faults 20 in the SRB material 18. FIG. 1F is a cross-sectional view of the device 10 in the gate width (W) direction of the device, while FIG. 1G is a cross-sectional view taken through one of the fins 16 in a gate length, current-transport direction (L) of the device 10.
In the ART process, the trench 14T is made deep enough (e.g., an aspect ratio of at least 2, but it may be much larger, in order for the ART process to work) such that defects 20 generated in the material grown within the trench 14T, in this case the SRB material 18, will be trapped at or near the bottom of the original trench 14T and in the sidewalls of the trench 14T positioned slightly above the interface between the substrate material 12 and the SRB material 18. The amount of defects 20 generated and the propagation of such defects 20 will depend upon the crystal orientation of the substrate 12. The intent of the ART process is that, while defect-containing material is present at or near the bottom of the trench 14T, the uppermost portions of the SRB material 18 will be substantially defect-free, as shown in FIG. 1E. However, as it relates to the specific task of forming fin structures for a FinFET device, the ART process has significant drawbacks due to the three-dimensional nature of the fin structures. The ART process works fairly well in trapping the defects 20 that propagate in the gate width direction W—see FIG. 1F—wherein the defects 20 engage the sidewalls 14S of the trench 14T. However, as shown in FIG. 1G, defects 20 that propagate in the gate length direction L can and do propagate all the way to the upper surface 18S of the SRB material 18, because in the middle regions of trench 14T there is no sidewall to stop the propagation of the defects 20 in the gate length direction.
FIG. 1H depicts the device 10 after the channel semiconductor material 22, e.g., silicon-germanium, silicon, or germanium, is grown on the defect-containing SRB material 18. Ideally, the channel semiconductor material 22 will be as defect-free as possible. However, due to the propagation of the defects 20 in the gate length directions, and the presence of those defects 20 at the surface 18S of the SRB material 18, the defects 20 may continue to propagate into the channel semiconductor material 22, as reflected by the dashed lines 20A in FIG. 1H. As a result, the channel semiconductor material 22 may contain more defects than would otherwise be desirable, and the presence of such defects in the channel semiconductor material 22 may reduce or limit the performance capability of the FinFET device 10.
The present disclosure is directed to various methods of forming alternative material fins with reduced defect density for a FinFET semiconductor device that includes performing an ion implantation/anneal defect generation process that may solve or reduce one or more of the problems identified above.